The present invention relates to techniques for the graphical analysis and manipulation of circuit timing requirements, and more particularly, to techniques for graphically displaying waveforms for timing signals in a circuit analysis tool that allows users to more easily verify the proper operation of a circuit.
The proper operation of a circuit design can be verified by simulating the circuit design using an electronic design automation (EDA) tool such as PrimeTime from Synopsis. An EDA tool can test a circuit design to ensure that the circuit operates according to user specified constraints.
User constraints may include timing constraints. Timing constraints, for example, can include time limits for the propagation of signals between circuit elements. The time limits may be selected to ensure that the overall circuit design operates according to user requirements.
An EDA tool can test a circuit design and output data indicating timing delays between signals propagating through the circuit design. Quartus™ II is an example of a prior art EDA tool that is used to test programmable integrated circuits such as programmable logic devices. An EDA tool can test or analyze the proper timing operation of a circuit as part of its placement, routing and synthesis netlist manipulations as well.
All references herein to circuit simulation tools, or timing analysis tools, should be understood to include all tools that perform verification of the circuit design, by either, dynamic simulation of signal levels at all nets in the list, or static computation of propagation delays traversing paths on the netlist. This applies to verification tools and techniques used as part of netlist optimization, synthesis, placement and routing EDA tools in the overall EDA design processing flow.
Quartus™ II analyzes a circuit design and outputs timing data. The timing data can include information such as the duty cycle and period of clock signals used in the circuit design, the clock skew between a clock source and a circuit element in the circuit design, the offsets between each clock signal, and the time points that active edges in the clock signals occur. An active edge in a clock signal is a rising or falling edge that triggers a circuit function (e.g., causes a latch to capture an incoming signal). Quartus™ II displays the timing data output in text format.
Quartus™ II displays the timing data in a text format that is difficult for users to understand and apply. Quartus™ II does not output timing data in a way that clearly focuses on relationships between relevant portions of the signals.
Quartus™ II also does not allow a user to easily determine if he is analyzing a relevant portion of a signal, because Quartus™ II does not indicate what the relevant portions of the signals are. A user is often forced to perform complex hand calculations to determine the relevant timing information based on the timing data output by Quartus™ II.
Therefore, it would be desirable to provide techniques for organizing and displaying timing data from an EDA tool that allows users to easily extract, analyze, and manipulate relevant portions of the timing data.